| System Features
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| Subrack dimensions
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722 mm (H) x 497 mm (W) x 295 mm (D)
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| Switching capacity
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Packet: 160 Gbit/s and TDM: 200 Gbit/s (higher order), 20 Gbit/s (lower order)
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| Service slots
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15 slots for processing boards and 16 slots for interface boards
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| Highly reliable design
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1+1 hot backup for power supply modules, system control boards, cross-connect and synchronous timing boards
Redundancy protection for fan modules
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| Supported interfaces
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Packet transport interfaces
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E1, ch STM-1, ATM STM-1, FE/GE/10GE
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| MSTP INTERFACES
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STM-1/4/16/64, E1/E3/E4/T1/T3, FE/GE/10GE, DDN, IMA/ATM, FEC/EFEC interface, E1 optical interface, SAN, Video
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| PCM interfaces
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FXS/FXO, 2/4 wire/E&M
V.35/X.21/V.11/V.24/V.28, RS232/422
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| WDM INTERFACES
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40-channel DWDM interfaces, compliant with ITU-T G.694.1
8-channel CWDM interfaces, compliant with ITU-T G.694.2
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| Networking Mode
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Supporting pure packet，hybrid (packet + SDH) or SDH networking
Supporting WDM networking
Supporting single-fiber bidirectional transmission
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| Power Supply
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-38.4~ -72V DC; 110/220V AC (External module)
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| Operation Environment
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Temperature Relative Humidity
Long term: 0°C ~ 45°C 10% ~ 90%
Short term: -5°C ~ 55°C 5% ~ 95%
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| Packet Transport Features
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| Service features
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E-Line and E-LAN
QinQ
MPLS-TP based VPWS and VPLS
Multi-section pseudo-wire (MS-PW)
TDM PWE3: CESoPSN and SAToP, compression of idle timeslots
ATM/IMA PWE3
ETH PWE3
IGMP SNOOPING V2
Blacklist, Broadcast packet suppression, ACL
VLAN SWAP
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| QoS features
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Hierarchical QoS scheduling and traffic shaping
DiffServ mode based on traffic classification
Simple traffic classification, complex traffic classification, per hop behavior (PHB), and ACL
Committed access rate (CAR)
PQ scheduling priority, weighted fair queuing (WFQ) and PQ+WFQ queuing
Tail drop and weighted random early detection (WRED)
Eight priority queues
Shaping based on port scheduling priority
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| Hardware-based OAM
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MPLS OAM
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LSP/PW OAM:
FDI, BDI
CV, FFD, TraceRoute, Ping
CES PW VCCV
LM, DM
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| MPLS-TP OAM
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LSP/PW OAM:
CC, LB, LT
AIS, RDI
LM, DM
LCK, TST
CSF
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Section OAM:
CC, LB
RDI
LM, DM
LCK, TST
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| Ethernet OAM
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ETH-CC(Continuity Check)、ETH-Loopback、ETH-Link Trace
Remote Loopback、Remote Fault Detection
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ATM OAM
RMON(RFC 2819)
Flexible design with multiple protocols
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|
Carrier-class protection
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LSP/PW Linear protection
MPLS-TP Ring protection
Anti multifailure protection based on MS-PW
Link aggregation group (LAG) protection
Multi-chassis link aggregation group (MC-LAG) protection
Dual-homing protection
LPT
STP/RSTP/MSTP
IMA protection
1+1 and 1:1 Linear MSP
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| Clock synchronization
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Two external clock inputs/outputs (2 MHz or 2 Mbit/s)
Two external time signals（1pps+TOD）
Adaptive clock recovery (ACR)
Synchronous Ethernet
IEEE 1588v2
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| MSTP Features
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| Carrier-class protection
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Mesh Protection and restoration（ASON）
Distributed restorable rerouting protection
5-level service dedicated protection scheme based on different SLA: Diamond, Gold, Silver, Copper and Iron services
SDH Network Protection
2/4 fiber MS-SP Ring; 1+1, 1:n (n<=14) Linear MSP; SNCP/SNCMP/SNCTP; Fiber shared virtual path protection; Fiber shared MS-SP Ring; DNI (ITU-T G.842)
Service Protection
Ethernet: RPR, RSTP, LAG/DLAG/PPS/BPS
ATM: VP-RING, PPS/BPS
Electrical Interface Protection
1:N tributary protection for E1/T1, E3/T3, E4, STM-1(e) and FE
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| Multi-service Transport Features
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Ethernet Over SDH
GFP/LAPS/VCAT/LCAS
L2 switch, 64 aggregation directions for powerful Ethernet convergence
Mapping granularity, VC-12-nv/VC-3-nv, and VC-4-nv
Point to Point LPT, Point to Multi-point LPT
MPLS and Stackable VLAN for L2 VPN
4/8-level CoS, CAR based on 64K granularity
IEEE 802.3ah, 802.1ag
RPR
Automatic topology discovery
3-level CoS , A(A0/A1) / B(B-CIR/B-EIR) / C
Steering/Wrapping/Steering + Wrapping protection scheme guarantee 50ms switching
Spatial reuse of bandwidth with fairness algorithm
Integrated MPLS with RPR to provide VLL/VPLS service
ATM
Support 2M, 34M, 155M, 622M ATM and IMA E1
support up to 93 IMA group & 189 E1s
Others
Support FC/ESCON/DVB-AS/ HD-SDI/SD-SDI
Support DDN(Nx64K) and Framed E1
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| Clock synchronization
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Two external clock inputs/outputs (2 MHz or 2 Mbit/s)
Line clock source
Tributary clock source
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